Jeonbuk National University (JBNU), Division of Electronics and Information Engineering, PhD candidate Hyun-gyu Kim (supervisor Ki-hyun Kim) received the Best Paper Award at the international conference 'IEEE TENCON 2025' organized by the Institute of Electrical and Electronics Engineers (IEEE).

IEEE TENCON is the largest international conference in the Asia–Pacific region where the latest research results in fields such as electrical and electronic engineering, semiconductors, artificial intelligence, communications, and control are presented. It is organized by the Institute of Electrical and Electronics Engineers (IEEE), the world’s leading scholarly and standards organization in electrical and electronic engineering with over 400,000 members in more than 160 countries. IEEE TENCON is an international event where hundreds of papers are presented annually by researchers from more than 20 countries.

The paper presented by PhD candidate Hyun-gyu Kim, titled "Design of Highly Stackable Charge Trap-Based 3D DRAM," reported research results on a next-generation 1T 3D DRAM capable of high integration, low power consumption, and high-speed operation that overcomes the structural limitations of conventional DRAM. The proposed device employs a 1T structure without a capacitor, achieving excellent data retention characteristics, high integration density, and efficient heat dissipation performance. The study also demonstrated that high-speed, low-power operation is possible in Charge Trap-based memory by using a Schottky contact formed through a metal silicide process and by adjusting the ONO dielectric thickness.

Hyun-gyu Kim said, "This research is significant in that it presents a new memory architecture that overcomes the integration limits of next-generation memory semiconductors and can be applied to various fields such as AI and high-performance computing. It is an example that shows the JBNU semiconductor research team has world-class technological competitiveness."

This study proposed a new memory architecture capable of overcoming the integration limits and process complexity of conventional DRAM, and it is expected to become a core foundation for the future development of next-generation semiconductor technologies for AI and high-performance computing. The research team plans to continue research on the development and commercialization of silicon-based next-generation 3D memory devices.

This research was supported by the Next-Generation Intelligent Semiconductor Technology Development Project (RS-2025-02653773) and the Phase-4 BK21 Project.